Post by surapaneni Vathsalya

🚀 Just completed RTL-to-GDSII flow for a 2×2 Systolic Array Matrix Multiplication Accelerator! Built a hardware accelerator with 4 parallel MAC units for 2×2 matrix multiplication. The design uses 8-bit fixed-point arithmetic with an FSM-based control unit. What I did: ▸ RTL Design — Verilog with modular MAC units ▸ Verification — Self-checking testbench ▸ Synthesis — Yosys with Nangate45 PDK ▸ Physical Design — Complete OpenROAD flow: floorplan, placement, CTS, routing Results: ✅ Setup Slack: met ✅ DRC Clean | 0 Routing Overflow ✅ 2,223 instances | 2.58 mW | 2,922 µm² ✅ 4-level H-tree clock | 137 sinks | 0.01 ns skew Full code and results: https://lnkd.in/d9ZeRJ6V #VLSI #PhysicalDesign #OpenROAD #RTL #HardwareAcceleration #SystolicArray #EDA #Semiconductor