Post by Snehita Patta

🚀 Turning theory into implementation! What started with learning that UART is one of the most widely used serial communication protocols evolved into designing and simulating a complete "FSM-Based UART Communication System with FIFO Buffer" using Verilog HDL. ✨ Key Features: 🔹 Configurable Baud Rate Generation 🔹 FIFO Buffer for Data Storage and Flow Control 🔹 Busy Signal for Transmission Status Monitoring 🔹 Transmission Counter for Tracking Data Frames 🔹 Parity & Framing Error Detection 🔹 Functional Verification using Vivado Simulation 🔗https://lnkd.in/gD8569Jz Building this project provided valuable hands-on experience in RTL Design, UART communication, FPGA development, and hardware verification. #Verilog #FPGA #VLSI #UART #FIFO #RTLDesign #DigitalDesign #Vivado #ElectronicsEngineering #HardwareDesign