Post by Siemens EDA (Siemens Digital Industries Software)

SoC complexity is scaling faster than traditional yield methods can handle. As transistor density increases and timelines shrink, "noise" in diagnosis data becomes a primary bottleneck. If root causes are not isolated quickly, manufacturing excursions stall the yield ramp and delay time-to-market. Our Yield Learning team, led by Marc Hutner, is focusing on three solutions to break these bottlenecks: 🔷 Faster diagnosis at scale — Tessent Diagnosis cuts cycle time by 50% with dynamic partitioning and scales volume scan diagnosis 10X, using just 20% of the typical memory footprint. 🔷 Accelerated silicon bring-up — Tessent SiliconInsight automates ATPG, EDT, BIST, and IJTAG characterization in a single environment. ATE-Connect technology eliminates the communication gap between test floor and ATE — shortening the path to production. 🔷 Root cause isolation before physical FA — Tessent YieldInsight applies machine learning to separate systematic yield limiters from diagnosis noise. Statistical analysis identifies root causes in days, not months — before a single device goes to physical failure analysis. Watch the 1-minute video below to see how these solutions streamline the path from silicon bring-up to high-volume production.

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