Post by Shiwank Gupta

🚀 Day 6/14 Completed: Entering the Domain of Memory Chains & Digital Timers! ⏱️💻 After locking down the single-bit D-Flip Flop yesterday, today was all about scaling up. Single bits are rarely processed alone in modern semiconductor architectures; they are grouped, shifted, and counted. Today, I engineered Multi-Bit Sequential Logic architectures. 🛠️ What I Built & Verified at the RTL & Netlist Level: 1️⃣ 4-Bit SISO & SIPO Shift Registers: Designed the hardware logic that forms the backbone of serial communication protocols (like UART, SPI, and I2C). Synthesizing this in Quartus provided visual proof of the Verilog concatenation operator translating directly into chained D-Flip Flops. 2️⃣ 4-Bit Synchronous Up-Counter: Engineered a digital timer using sequential arithmetic logic. The Quartus RTL viewer clearly demonstrated how the tool infers physical Hardware Adders and Multiplexers to execute the synchronous reset and count + 1 logic. 🚧 The Verification Challenge (Top-Level Integration): Instead of running isolated tests, I merged the simulation environment in ModelSim to observe all three engines running concurrently. Tracking the transcript and waveforms side-by-side perfectly validated the shift logic and the physical transition from xxxx (unknown initial state) to deterministic values. Next up: Combining these memory chains with combinational logic to build the actual decision-making brains of a chip—Finite State Machines (FSMs). Follow the 14-day tape-out pipeline as I continue building complex hardware from scratch! 🚀 #VLSIDesign #RTL #Verilog #DigitalDesign #Semiconductors #FPGA #ASIC #HardwareEngineering #ModelSim #Quartus #ChipDesign Intel VLSI Technology VLSI FOR ALL Pvt Limited Anupoju Surya Pavan Kumar RTL Design Verification Engineer Design Verification kunal ghosh (vlsisystemdesign.com) Siemens Digital Industries Software VLSI Learning Community Explore VLSI NXP Semiconductors Marvell Technology