Post by Racyics

At embedded world conference 2026, our colleague Alexander Persicke will present a wafer-level test concept for the 𝐔𝐂𝐈𝐞 𝐢𝐧𝐭𝐞𝐫𝐟𝐚𝐜𝐞, focusing on robust strategies for high-speed die-to-die communication in his presentation: “𝐖𝐚𝐟𝐞𝐫-𝐋𝐞𝐯𝐞𝐥 𝐓𝐞𝐬𝐭 𝐂𝐨𝐧𝐜𝐞𝐩𝐭 𝐟𝐨𝐫 𝐭𝐡𝐞 𝐔𝐧𝐢𝐯𝐞𝐫𝐬𝐚𝐥 𝐂𝐡𝐢𝐩𝐥𝐞𝐭 𝐈𝐧𝐭𝐞𝐫𝐜𝐨𝐧𝐧𝐞𝐜𝐭 𝐄𝐱𝐩𝐫𝐞𝐬𝐬 (𝐔𝐂𝐈𝐞) 𝐈𝐧𝐭𝐞𝐫𝐟𝐚𝐜𝐞” 📅 𝐓𝐮𝐞𝐬𝐝𝐚𝐲, 𝟏𝟎 𝐌𝐚𝐫𝐜𝐡 𝟐𝟎𝟐𝟔 🕒 𝟏𝟒:𝟒𝟓–𝟏𝟓:𝟏𝟓 📍 𝐑𝐨𝐨𝐦 𝐁𝐮𝐝𝐚𝐩𝐞𝐬𝐭 (Session 4.2: Chiplets – Certification, Validation & Test (powered by UCIe)) Manufacturing chiplet-based systems requires 𝐊𝐧𝐨𝐰𝐧 𝐆𝐨𝐨𝐝 𝐃𝐢𝐞𝐬 (𝐊𝐆𝐃𝐬)  prior to assembly. Otherwise, a single defective chiplet can lead to high scrap costs and reduced final yield. A robust wafer-level test strategy is therefore a key enabler for cost-effective, high-volume chiplet integration, especially when targeting high-speed interfaces such as 𝐔𝐂𝐈𝐞. In this presentation Alexander introduces a 𝐩𝐫𝐞-𝐩𝐚𝐜𝐤𝐚𝐠𝐞 𝐭𝐞𝐬𝐭 𝐜𝐨𝐧𝐜𝐞𝐩𝐭 𝐟𝐨𝐫 𝐔𝐂𝐈𝐞, the open industry standard for high-speed, interoperable die-to-die communication in chiplet-based systems. The concept translates the UCIe architecture into practical wafer-level test domains, mapped to established, manufacturable test methods suitable for high-speed die-to-die interconnects. The approach combines: • logic testing • loopback-based built-in self-test (BIST) • dedicated component-level tests for critical analog blocks We look forward to seeing you at the session and to continuing the discussion at our booth. 𝐞𝐦𝐛𝐞𝐝𝐝𝐞𝐝 𝐰𝐨𝐫𝐥𝐝 𝟐𝟎𝟐𝟔 | 𝐇𝐚𝐥𝐥 𝟒 | 𝐁𝐨𝐨𝐭𝐡 𝟒-𝟓𝟓𝟐 https://lnkd.in/dSbrVKZe #Racyics #Innovation #EmbeddedWorld2026 #Chiplets #UCIe #Test #BIST