Post by Jaemin Baek

As the GLVS Team Leader for the F-26 Formula SAE Electric vehicle, I conducted bench testing for the F-26 Vehicle Control Circuit Rev.01 and ACC Circuit Rev.01. The purpose of this test was not only to confirm whether each circuit operated, but also to identify unstable logic behavior before full vehicle integration. Since these circuits are directly related to startup sequencing, precharge control, inverter enable logic, dashboard indication, and fault response, even small timing or reference-voltage issues could affect system reliability. During the VCU test, I identified several logic-level issues. One issue was related to the reset signal for SR-latch initialization. The initial logic used an OR gate and an optically isolated relay output, but the node voltage remained around 1.1–1.23 V due to the internal diode structure, which caused the reset condition to be ignored. To solve this, I revised the reset input structure so that the logic would receive a clear 12 V-level signal. Another issue was found in the delay timing circuit. The target delay was 3.54 s, but the measured delay was approximately 0.5 s. After reviewing the circuit, I found that the resistor network used for the delay setting had been selected incorrectly. I plan to recalculate the timing components using the manufacturer’s recommended design tool and verify the corrected delay through another bench test. I also found unstable behavior in the binary comparator logic used for RTD and BSPD-related timing. Since the comparator output changed unpredictably during counter transitions, I reviewed the reference-bit configuration and the interaction between the binary counter and comparator. The next revision will simplify the reference condition or move part of the delay judgment into the STM logic to improve stability. During the ACC and Tractive Battery Circuit test, I also reviewed the LF398 sample-and-hold circuit used for precharge voltage comparison. The initial design did not fully reflect the datasheet’s supply and logic reference requirements, which caused incorrect behavior between sampling and holding modes. I also confirmed that the ceramic hold capacitor produced a larger voltage drop than expected, while a film capacitor showed significantly better hold performance. Based on this result, the next revision will use a more appropriate hold capacitor and corrected reference configuration. Through this test, I was able to move from schematic-level assumptions to actual circuit behavior. The process helped me better understand reset logic, timing circuits, comparator behavior, sample-and-hold characteristics, and the importance of validating datasheet assumptions through physical testing. This was a useful reminder that a circuit is not complete when the schematic looks correct. It is complete only after the actual behavior is measured, understood, and revised. #FormulaSAE #ElectricVehicle #GLVS #CircuitDesign #PCBDesign #VehicleElectronics #Testing #MotorsportEngineering