Post by imec

Press release - At the IEEE/JSAP Symposium on VLSI Technology & Circuits, imec and Sony Semiconductor Solutions present a new module for high-density backside connectivity, a key enabler for 3D stacking and backside functionalization. The approach is built around a self-aligned local backside dielectric isolation step, enabling sub-100nm through-silicon vias that connect the fine-grained wafer frontside and the less densely structured backside. Starting from narrow frontside vias, the module allows a transition to wider TSVs, reducing aspect ratio and simplifying metallization. Compared to conventional via-middle approaches, this results in lower resistance, a larger overlay window, and lower leakage The scheme enables new 3D integration schemes for a variety of use cases, including advanced logic and memory applications Read the full press release: https://lnkd.in/emVYWDpC