Post by Frank Schirrmeister

Great article by Brian Bailey over at Semiconductor Engineering on "Re-Architecting AI For Power." He is pondering the question whether AI is using too much power. Some people think so, and believe the easy gains in power reduction have already been made. I was part of the discussion together with Marc Swinnen, Jason Lawley, Doyun Kim, Rich Goldman, Maxim Khomiakov, diptesh nandi, Prem Theivendran, Benjamin Prautsch, Jeff Roane, and Andy Nightingale. I personally think that there are many items we as industry still have to work on. "[The complexity of interactions between the workload, the architectures, the transactions to the memory storage have simply become too intricate for people to predict. There still will be some components where spreadsheets will help you to identify the impact of a cache on how much traffic will pass across a chip or chiplet boundary, which may consume more power. You may still do a back-of-the-envelope calculation and use stochastic models. But the interactions are so complex that people require AI workloads to be run on your target architecture so that you’re confident you’re doing the right things from a performance perspective.” #Synopsys #AI #LowPower https://bit.ly/45PFday