Post by Entra Innovations

We’re hiring for our growing silicon design team at Entra Innovations, incubated at IIT Dharwad. ​ Open roles: Technical Lead – RTL Design; Project Staff – Analog Layout, DFT and STA. Technical Lead: 5–10 years experience in ASIC/FPGA RTL design, and SoC integration; prior team/technical leadership preferred. Project Associate: 2-3 Years of experience in Physical Design or DFT Project Assistants: Bright 2024/2025 EE/ECE grads with solid fundamentals in CMOS, digital design, and an interest in analog layout, DFT or STA. Location: Dharwad (with close collaboration with IIT Dharwad). ​ Interns (unpaid): Open positions for - FPGA Design, RTL Design, Firmware (RISC-V), Embedded System Design (HW/SW co-design) on a rolling basis. Preferred 4-6 months full time availability. If this sounds interesting, send your resume to [email protected] with the role in the subject line (e.g., “Technical Lead RTL – ”). Shortlisted candidates will be contacted for further discussion. Ritesh Belgudri, Dr. Nagaveni S Dr. Koteswararao Kondepu #hiring #semiconductors #VLSI #RTL #ASIC #FPGA #DFT #AnalogLayout #STA #PD