Post by Chad Wallace

High speed communications at 224Gbps and 448Gbps is more than just co-packaged optics; it requires a highly sophisticated SerDes transciever to get the data there. To scale in speed and performance, modern SerDes transceivers can no longer rely on simple analog circuits. Instead, they require massive architectural parallelization—using multi-rank time-interleaved ADC networks and charge-steering MUX trees—to support the data demands. However, parallelizing the datapath requires a robust clock distribution network to synchronize the data processing. Clock distribution is important because traditional buffer chains collapse your timing margins when you are managing picosecond-level skew and clock feedthrough across a giant die. I mapped out the entire high-speed wireline datapath from first principles, dissecting the architecture of DSP-based SerDes architectures and showing how impairments affect the system behavior. I also cover key novel architectures, including current-steering DAC nonidealities and the asynchronous SAR. After the paywall, I cover the clock distribution network and clock data recovery (CDR). I also write several other pieces related to high-speed SerDes scattered throughout the post such as PLLs, ADCs, and High-speed signal integrity; check them out as well. https://lnkd.in/g2ta_yse