Post by Cadence

There is often a mismatch between the advanced design of a chip and the data center infrastructure necessary to house that chip, says Sherman Ikemoto, Group Director of Business Development at Cadence. "All of the efficiency that you're getting out of very highly optimized chip design can't translate all the way up to the data center unless that gap is closed." In an in-depth Cool Vector Video-Podcast interview, Ikemoto describes how “the timescales to build chips, and to build the facilities that house the chips, are totally different. So there's this natural massive gap in the design chain.” Key takeaways from Ikemoto’s interview: • If data center developers are able to compress a 24-month AI factory standup to 18 or 16 months, that translates directly into billions of dollars of accelerated return. • For three decades, rack power density grew ~10% annually. In the AI era, it has jumped to 60–100% per year—an order-of-magnitude acceleration that fundamentally breaks traditional data center cooling technologies and design methodologies. Learn more: https://lnkd.in/exvei6KD

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