Post by ABI S S
M.E. VLSI Student at Kongu Engineering College | ECE | Aspiring VLSI Engineer | Cadence - Virtuoso, Innovus, Genus | Verilog | VLSI Frontend
🚀 Every Stable Voltage Has an Unstable Story Behind It. When I first started designing a CMOS Bandgap Reference Circuit, I thought the biggest challenge would be getting a 1.2 V output. I was wrong. The real challenge was understanding why it wasn't stable. There were moments when the output dropped below 0.55 V, resistor values had to be optimized repeatedly, PSRR plots refused to behave as expected, and I spent hours understanding why CTAT decreases while PTAT increases with temperature. Every simulation raised a new question, and every question pushed me deeper into the fundamentals of Analog IC Design. Instead of looking only for the correct output, I started asking: 💡 Why are three BJTs needed? 💡 Why should resistor ratios be carefully selected? 💡 How does a current mirror actually help in generating a stable reference? 💡 How can two voltages with opposite temperature characteristics combine to produce one temperature-independent voltage? Gradually, the answers came—not from textbooks alone, but from countless simulations, iterations, and debugging sessions in Cadence Virtuoso (gpdk90nm). Finally, seeing the Bandgap Reference remain nearly constant over temperature wasn't just a successful simulation—it was proof that understanding the fundamentals always pays off📈. This project has given me more than a reference voltage. It has given me a deeper appreciation for how precision analog circuits are built, where even a small change in a resistor or transistor can completely change the circuit's behavior. Every graph 📉, every failed simulation ❌, every correction 🔄, and every improvement 📚 strengthened my curiosity about Analog & Mixed-Signal IC Design. This is only the beginning, and I'm excited to keep exploring the world of VLSI, ASIC Design, and Semiconductor Engineering. ✨ Engineering isn't about getting the perfect result on the first attempt. It's about understanding why it wasn't perfect—and improving it one iteration at a time. #AnalogICDesign #VLSI #CMOS #BandgapReference #CadenceVirtuoso #ASIC #Semiconductor #ECE #Learning #EngineeringJourney #gpdk90nm
