Post by Abhi Chandra B
ECE Student | Aiming to be a VLSI Engineer | Digital Design • Verilog HDL • FPGA | Embedded Systems & IoT | Passionate About Semiconductor and Hardware Innovation
🔷 Built a Python-based EDA Regression Framework for RTL Verification One of the biggest challenges in VLSI development is running and verifying multiple Verilog modules consistently. So my friend Sujeet, and I built an automation framework that solves exactly that. What it does: → Auto-compiles Verilog modules using Icarus Verilog → Runs simulations automatically → Parses PASS/FAIL results from testbench output → Generates a professional HTML regression dashboard → Watch mode — auto-reruns on every file save → JSON reports for CI/CD integration The result? A single command replaces hours of manual compile → simulate → check cycles. python automate.py --root . run --all 16 ALU tests. 0 failures. 0.23 seconds. This framework now runs across my entire 8-repo VLSI portfolio — from basic logic gates to a 16-bit pipelined RISC processor. Framework repo: https://lnkd.in/dBSHx7fh VLSI Portfolio: github.com/abhichandra586 ⭐ Full credit to Sujeet for designing and building the framework architecture. My contribution was the RTL integration, module registry, and testbench standardization. Github: github.com/Sujeet-Kona LinkedIn: https://lnkd.in/d747dTu9 #VLSI #Verilog #Python #EDA #RTLDesign #DigitalDesign #Automation #IcarusVerilog #ECE #Semiconductor
