New York, New York, United States
I’m a hardware engineer focused on ASIC, Design Verification (DV), Computer Architecture, RTL Design, and SoC. At Synopsys, I used Timing Constraint Manager (TCM) and PrimeTime to review, validate, and debug customer timing constraints for signoff. I built an automated SDC lint testcase suite (Make/Tcl) to surface violations like missing clock propagation, false-path misannotations, and exclusive clock domain issues. On the DV/architecture side, I designed and verified a 3-way superscalar, P6-style RISC-V OoO core (I/D caches, LSQ, early branch resolution) with a 15 ns clock, ~1.5 CPI on loop-heavy code, and ~70% branch-prediction accuracy vs. 16% baseline. Open to: Design Verification / STA / RTL roles Toolbox: SystemVerilog, UVM, SVAs, TCM, PrimeTime, Virtuoso, VCS, Verdi, Innovus, Python/C++.
Performed static timing analysis with Timing Constraint Manager (TCM) to validate and debug timing constraints, supporting signoff across complex SoC designs. Developed an SDC lint testcase suite with automated scripts, enabling detection of violations (e.g., false paths, missing clocks, exclusive domains) and serving as a reference for customers and internal teams. Authored a complete End-to-End User Guide integrating Fusion Compiler, Formality, PrimeTime, RTLA, and TCM, now used as the onboarding resource for new constraint verification flows.
Designed and implemented an LVDS communication board in SystemVerilog with PCIe and AXI bus integration for high-speed data transfer. Built verification testbenches and used Xilinx and Tcl scripting to ensure robust functionality.