United States
I am a Hardware Engineering Manager at NVIDIA, leading multidisciplinary teams responsible for the design and verification of GPU and AI accelerator hardware platforms. My professional journey spans hands-on roles in hardware design and verification at global semiconductor companies, where I worked on ASIC and SoC development, RTL design, functional verification, and silicon bring-up. Over time, I transitioned into leadership roles, managing teams across architecture, design, and verification to deliver complex, high-impact hardware products at scale. I am passionate about building resilient engineering organizations, developing technical talent, and translating complex hardware challenges into reliable, manufacturable products.
Lead the hardware design and verification team (10-30 people) Coordinate the architecture, RTL design, verification, physical design, and test engineering teams. Develop design specifications, design processes, and quality objectives. Monitor the chip design cycle's progress, risks, resource allocation, and technical roadmap. Drive design reviews, verification reviews, and status reporting. Collaborate with the software and system architecture teams to ensure overall platform functional consistency.
Responsible for functional and integration verification strategies for mobile SoC core modules Designed automated verification platforms and coverage-driven verification solutions Used SystemVerilog and UVM for testbench building and script development Guided intermediate and junior engineers in performing verification tasks Organized cross-team root cause analysis and defect remediation coordination
Participate in the digital hardware design of network and communication SoCs Write RTL (Register Transfer Level) code and perform module-level cell verification Participate in static timing analysis (STA) and design optimization Verify designs using FPGA prototyping and submit design changes Collaborate with layout engineering and verification teams to ensure design manufacturability
Supports test environment setup for CPU/SoC verification teams. Writes test stimuli using Verilog/SystemVerilog. Performs chip functional verification, collects test data and defect reports.