Hsinchu County, Taiwan, Taiwan
**17+ Years of Semiconductor Expertise**: - Specialized in BEOL Process Integration, focusing on advanced interconnect and reliability - Experience at TSMC covering R&D to yield ramp-up from 28nm to 1.4nm nodes. - Skilled in process integration, yield enhancement, and program management. - Delivered solutions for BEOL/MEOL yield optimization. - **10+ Years of Leadership**: - Lead cross-functional teams in driving cutting-edge process and device development, ensuring alignment with scaling, performance, yield, and manufacturability targets. - Coordinate and manage R&D programs from early-stage pathfinding to process qualification, with a proven track record of project execution and timely delivery. - Support physical design/layout optimization through advanced layout methodologies to maximize speed, minimize power, and improve area efficiency. - Recognized for strategic planning and execution in high-pressure environments. - Published over 25 US patent. - Authored significant papers in IEDM 2021 and IITC 2012, demonstrating advanced interconnect and contact technology development - Earned 6+ awards, including Best Patent, and TSMC Idea Forum , for process innovations. Golden Trade Secret Award • 2023 Best Patent, TSMC – MEOL/BEOL Rc Reduction • 2019 Best Patent, TSMC – Low Capacitance Structure • Golden Trade Secret Award, TSMC – 2015, 2021, 2022, 2024 - **Key Achievements**: - Pioneered barrier-less contact integration and delivered N3 BEOL baseline with self-assembled monolayer (SAM) and post-ALD TaN plasma treatment, reduce V0/Vx via resistance by 50%. Skills: - Back-End-of-Line (BEOL) Yield Analysis - Project Management - Defect metrology analysis