Lehi, Utah, United States
My expertise - Integration/Device/Problem Solving/Team Working About me - I enjoy playing soccer, tennis, fishing outside of work. I love spending time with my family outdoors
• Working closely with Process team, Integration, Product team and BE testing to improve 3DxP Endurance/Reliability
• Optimize various technology nodes in collaboration with PI sustaining teams • Lead a cross-functional focus team of 10+ engineers, improved 20 nm NAND yield to be above mature yield (from 87% to 91%), and increased product lifetime by 2X (30,000 cycles qualified) • Won Intel Division Recognition Award due to tremendous contributions to Intel’s success, first time ever awarded to outside candidates by Intel • Coordinated a global focus team of 10+ engineers, eliminated probe fail due to X-ingot non-uniformity, and increased sub-20 nm NAND yield by 1.7% • Took on-line course of “Advanced MOS Device” from Arizona State University • Advancing the current and legacy technology nodes in collaboration with PI sustaining teams. • Working closely with YE, process groups, and PE to improve yield and address reliability issues. • Communicating between parent company Product Engineering teams to ensure the success of Fab 2 projects. • Monitoring probe data, parametric data, and proactively engaging in the design and evaluation of experiments to optimize designated part type/process node. • Responsible for incoming Silicon quality - Working closely with all Silicon vendor to identify/solve substrate silicon related yield/device issues
• Administered the 20 nm NAND Wordline module in a high volume manufacturing (HVM) environment • Identified and fixed 20 nm NAND technology problems improving yield by 15% • Determined the root-cause of Wordline CD mismatch, ensuring 100% successful technology transfer from R&D
Photo Process Engineer