New Delhi, Delhi, India
I'm an Electronics & Communication Engineering graduate from IIIT Delhi, currently working as an FPGA/RTL Design Engineer at OrVis Semi, where I build and verify production-grade digital systems on Xilinx FPGAs using Verilog. My recent work includes architecting a hardware-validated SPI-mode SDXC storage controller on Xilinx Spartan-7 — a 5-FSM shared-SPI system covering full initialization (CMD0→CMD8→ACMD41→CMD58 OCR/CCS detection), CMD17/CMD18 block reads with CMD12 stop, and CMD24 write — verified end-to-end via byte-exact write→readback UART hex-dump on real hardware. Alongside this, I architected a 7-stage Verilog streaming pipeline (Bayer→RGB→Grayscale) operating at 100 MHz, incorporating bilinear demosaicing, fixed-point RGB-to-Y8 conversion, and a bilateral filter with reciprocal-LUT normalization — hardware output validated via Python-based frame rendering on host PC. On the physical design side, I've executed the complete RTL-to-GDSII flow for a 2x2 Network-on-Chip router using Cadence Genus (synthesis), Tempus (STA), Conformal (formal equivalence checking), and Innovus (placement, CTS, routing) - taking a design from RTL all the way to GDSII generation. I'm a Cadence Scholarship Program Scholar - awarded to the top 1% of ECE students nationally - with hands-on exposure across Digital/RTL Design (FSM architecture, pipelining, CDC, SPI, UART, I2C), FPGA Platforms (Xilinx Artix-7, Spartan-7, Zynq, Basys3), Physical Design (Floorplanning, P&R, CTS, STA, Low Power Design), and EDA Tools (Cadence Innovus, Virtuoso, Genus, Tempus, Xilinx Vivado, ModelSim). I also actively share insights on FPGA design, VLSI, and semiconductor engineering with a growing community of 8,000+ followers on LinkedIn. Open to full-time opportunities in RTL Design, FPGA Engineering, or Physical Design at semiconductor companies working on SoC, ASIC, or FPGA platforms. [email protected]
FPGA/RTL Engineer | OrVis Semi (CMOS Imaging Semiconductor Startup) Building hardware-verified RTL on Xilinx Spartan-7 for real-world CMOS imaging applications. SD Card Controller (SPI Mode) Designed a multi-module Verilog SDXC controller covering full initialization (CMD0->ACMD41->CMD58), block read/write operations, and hardware-validated data integrity at 12.5 MHz. Implemented shared-SPI architecture with FSM-arbitrated ownership across 4 modules, 2-stage MISO CDC synchronizer, and 512-byte BRAM buffer. Debugged using Xilinx ILA, UART hex dump, and LED-mapped status indicators. AR0130 Image Processing Pipeline Architected a 7-stage real-time streaming pipeline at 100 MHz - bilinear demosaicing (3-line buffer, 3x3 sliding window FSM), fixed-point RGB-to-Y8 DSP conversion, and edge-preserving bilateral filter with reciprocal-LUT normalization. Output validated via Python UART readback on physical hardware. Isolated high-speed fabric from 115,200 baud UART using FIFO rate-matching buffer for CDC management. Tools & Skills: Verilog - Xilinx Vivado - Spartan-7 - ILA - Keysight DSO - SPI - UART - FSM Design - CDC - FIFO - Fixed-Point DSP
Guide - Prof. Pankaj Vajpayee (Director & CEO, IIITD-IC) • Actively fostering student entrepreneurship by identifying campus challenges, supporting project development, and coordinating with the Dean of Corporate Affairs for project approvals. • Organizing incubator events with industry founders and academic experts while managing and enhancing the center’s social media outreach to boost engagement.
Project Title: Understanding the effect of coherence of motion stimuli on the Amplitude of N300 ERP Guide: Prof. Sonia Baloni Ray • Built the experimental interface for random dot motion kinematogram using the Psychopy library. • Developed an algorithm for saliency modeling to establish the relationship in emotional expressions during facial communication. • Conducted in-depth analysis of EEG and eye-tracking methodologies using quantitative methods to investigate and identify neural correlates of attention.