Abdullah Yıldız

Design and Verification Engineering Team Member at YONGATEK

Istanbul, Türkiye

About

I work as a senior project lead at YONGATEK Microelectronics R&D. Before then, I was Prof. Sezer Gören's teaching and research assistant at RESys Lab (Reconfigurable and Embedded Systems Lab, URL: resyslab.github.io). Although I worked as a graduate research assistant more than 8 years, I was involved in different projects during that time that helped me to follow hot topics in industry. I have also gained a lot of engineering experience in various topics including reconfigurable hardware security, embedded systems, ASIC/SoC/FPGA design and implementation, CPU design, Design for Test (DFT), etc. thanks to my supervisors Prof. Sezer Gören and Prof. H. Fatih Ugurdag. Skills/Interests: RISC-V, Verification, ASIC/FPGA Synthesis, Static Timing Analysis, Design for Test (DFT), Linux, C, SystemVerilog, Embedded Systems.

Experience

  • Design and Verification Engineering Team Member at YONGATEK - Yonga Technology Microelectronics
    Oct 2019 - Present · 6 yrs 10 mos

  • Team Member at RESys Lab
    Feb 2011 - Present · 15 yrs 6 mos

  • Yeditepe University (Istanbul, Istanbul, Türkiye)
    • Research Assistant
      Feb 2011 - Aug 2019 · 8 yrs 7 mos

    • Teaching Assistant
      Sep 2012 - Jan 2019 · 6 yrs 5 mos

      Courses: Introduction to Digital Systems Digital System Design Computer Organization Operating Systems Design Embedded Systems Programming Analysis of Algorithms File Organization Algorithms and Computer Programming

  • Teaching & Research Assistant at Ozyegin University
    Sep 2010 - Aug 2012 · 2 yrs

    Courses: Digital Systems