Yee Tan

Ex-Manager, Yield Enhancement Defect Reduction at TSMC Washington

Portland, Oregon Metropolitan Area

About

Experience

  • Manager, Yield Enhancement & Defect Reduction at TSMC Washington
    Sep 2024 - Apr 2026 · 1 yr 8 mos

    Manager of 5 engineers and 10 shift technicians. Define and execute defect reduction and yield improvement for each modules. Report defect excursions on daily basis at operations meeting to senior leadership. Coach and develop engineers and technicians, promoting technical growth and knowledge sharing. Data Analysis Skills : JMP, Excel

  • Technical Manager, Product Yield at TSMC
    Apr 2012 - Sep 2024 · 12 yrs 6 mos

    Coach a team of engineers on CP yield improvement activities. Drive yield improvement activities through data analysis, identifying root cause and working closely with Process Integration and Process Modules. Also, resolve FT low yield and Line/Field returns issues. NTO ramp yield improvement projects. Work closely with customers to meet their yield demand. Data analysis and correlations using JMP and SAS-EG Fab Process Tool, Process recipe change, WAT, inline/offline measurements, defect scans data to identify yield problems. Use EFA/PFA to identify low yield root cause.

  • Senior Engineer, Yield Enhancement & Defect Reduction at TSMC Washington
    Sep 2009 - Apr 2012 · 2 yrs 8 mos

    Develop a standard step by step SOP for KLA 2138 and AIT-XP recipe optimization for defect sensitivity improvement and nuisnance reduction for technicians to follow. Work with module equipment managers for defect reduction activities for dry etch and PVD toolset.

  • Senior R&D Defect Engineer at Spansion
    Aug 2008 - Feb 2009 · 7 mos

    28-32nm 12-inch wafer R&D NOR flash fab, analyse defect data. Lead and work with Yield/Defect/Process/Integration engineers to troubleshoot defect problems and improve defect SPC charts. Hands-on experience on KLA defect tools and AMAT SEM.

  • Defect Application Support Engineer at Applied Materials
    2005 - 2008 · 3 yrs

    Lead H2H recipe development competition in 12-inch wafer 28-32nm node Bright-Field and Dark Field Wafer Defect Inspection UVision and Complus applications experts, hands on application on SEMVision.