Yash Verma

Electronics (VLSI) Undergraduate | Pre-Final Year (B.E. 2027) | Thapar Institute of Engineering & Technology | Former Intern at IIT Delhi

New Delhi, Delhi, India

About

As a pre-final year B.Tech student at Thapar Institute specializing in Electronics (VLSI Design and Technology) Engineering, I am building a strong foundation in core Digital VLSI, with a focus on RTL design and verification. Through my coursework and projects, I have gained hands-on experience with Verilog/VHDL and the fundamentals of the ASIC and FPGA design flows. I am a keen learner, passionate about the challenges of modern chip design, and committed to continuously developing my skills in this dynamic field. I am actively seeking an internship in Digital Design or Verification to contribute to a team, apply my knowledge, and grow as a VLSI engineer.

Experience

  • Executive Committee at URJA TIET
    Jan 2025 - Present · 1 yr 7 mos

  • Entrepreneurship Development Cell, TIET (Patiala, Punjab, India · On-site)
    • Core
      Nov 2024 - Present · 1 yr 9 mos

    • Member
      Sep 2023 - Nov 2024 · 1 yr 3 mos

  • Under-Secretariat General (USG) at Thapar MUN Society
    Jul 2024 - Present · 2 yrs 1 mo

  • Executive Member at Thapar ACM Student Chapter
    Nov 2023 - Present · 2 yrs 9 mos

  • Member at LEAD Society TIET
    Oct 2023 - Present · 2 yrs 10 mos