United States
• Physical Design/Implementation engineer with 7 years of experience in RTL to GDSII implementation of UCIE/HBM testchips and high-performance CPU cores, timing analysis, physical verification, IR analysis and high frequency clock distribution. • Testchip Lead responsible for driving successful tapeouts of UCIE/HBM testchips across multiple technology nodes. • Expertise in synthesis, floorplanning, placement, clock tree synthesis, routing, timing closure, EMIR, and physical verification. • Expertise on tools like Fusion Compiler, ICC2, Prime Time, ICV, StarXT, Design Compiler, Redhawk and Calibre.