Yash Chaurasia

Lead Engineer, Silicon Labs, India

Mumbai, Maharashtra, India

About

Digital design engineer proficient with dedicated IP designs, IP and SOC integration and BUS level security Currently working at analog front end design and low power architecture Experience with chip and fpga validation

Experience

  • Silicon Labs (5 yrs 5 mos)
    • Lead Engineer
      Apr 2026 - Present · 4 mos

    • Senior Design Engineer
      Mar 2024 - Apr 2026 · 2 yrs 2 mos

    • Design Engineer I
      Jul 2021 - Apr 2024 · 2 yrs 10 mos

  • Research Intern at Bhabha Atomic Research Centre
    Jan 2018 - May 2018 · 5 mos

    1. Got assigned to the team responsible for designing a wireless power transfer module for an implantable device to treat dystonia 2. Collaborated with the team to find out the best feasible bio compatible material for the enclosure of implantable device 3. Actively participated in writing firmware for the on board microcontroller embedded onto the implantable device which taught me how to work with new software and how to efficiently read a technical document and datasheet 4. Collaborating with the country's best engineers and scientist taught me how to approach a problem

  • Project Intern at Nuclear Power Corporation of India
    May 2016 - Jul 2016 · 3 mos

    1. Since being at an active nuclear power plant, I was not allowed to operate anything but I had a good exposure on how the control and management of such a sensitive plant is being done. 2. Learnt about various sensors involved in a nuclear reactor.