Hisar, Haryana, India
Electrical Engineering undergraduate at IIT Gandhinagar specializing in custom digital logic, computer architecture, and hardware acceleration for AI/ML workloads. I focus on bridging the gap between deep learning algorithms and physical silicon, architecting systems that are optimized for power, precision, and resilience in resource-constrained environments. Currently, my research involves contributing to an ISRO-mentored initiative focused on fault-tolerant, radiation-resilient AI inference pipelines for satellite systems. My hands-on experience spans from designing custom arithmetic logic (Posit FPU) and microprocessors (RISC-V) to deploying quantized neural networks on edge FPGAs. Top 5 Technical Skills: 1. SystemVerilog & RTL Design 2. Computer Architecture (RISC-V) 3. FPGA Prototyping (Xilinx Vitis/Versal) 4. Hardware-Software Co-design 5. Embedded Machine Learning & Quantization I am passionate about building robust hardware architectures from the transistor level up to the application layer. Always open to connecting with engineers, researchers, and recruiters discussing RTL design, ASIC/FPGA engineering, and the future of AI hardware acceleration.
ISRO-Mentored AI Hardware & Architecture: • Contributed to an ISRO-mentored initiative to develop fault-tolerant, radiation-resilient onboard AI/ML inference pipelines for satellite systems. • Architected a custom FPU for Posit(16,2) arithmetic in SystemVerilog, achieving higher dynamic range and precision for ML hardware acceleration compared to standard IEEE-754 floats. • Collaborated on the deployment of end-to-end inference (ResNet-50, MobileNet, YOLO, U-Net) on Xilinx Versal AI Core ACAP & Zynq UltraScale ZCU104, applying Post-Training Quantization (PTQ) via Vitis AI 3.0 in Docker. • Co-developed a custom AXI-stream fault-injection IP for ZCU104 DDR4 to simulate MBU, SBU, and SEFI radiation faults, evaluating bit-flip impact on model accuracy and benchmarking against 9 satellite-image distortion types. Core Systems & Robotics: • Designed and verified a RISC-V PCPI Coprocessor and an RV32I core in Verilog, focusing on RTL modularity, pipeline stages, and hardware-software co-design for instruction set extension. • Architected a scaled Autonomous Underwater Vehicle (AUV) prototype specialized for marine human detection, engineering robust interfaces to seamlessly integrate real-time computer vision algorithms with physical marine sensor payloads. Photonics & Applied AI: • Developed an AI keyword recognition system using Fiber Bragg Grating (FBG) contact sensors for acoustic vibration capture. • Implemented optical signal processing and Librosa-based feature extraction, achieving 97.14% validation accuracy via an Audio Spectrogram Transformer (AST).
• Worked under Prof. Arup Lal Chakraborty on a UAV-mountable optical sensing system for H2O and CH4 detection via Tunable Laser Diode Absorption Spectroscopy (TLDAS). • Designed and implemented an IC-based laser driver (MTD415TE + MLD203CHBE) for an Eblana DFB laser (~1392 nm); iterated schematics across KiCad, EasyEDA, and Autodesk Eagle. • Assembled a complete sensing node integrating an InGaAs photodiode, GPS (Quectel L80), 4G HAT, and Raspberry Pi 4B with real-time waveform acquisition via UART. • Built an FPGA-based digital lock-in amplifier (LIA) on Xilinx Artix-7 and Red Pitaya (Zynq 7010 SoC) implementing 10/20/40 kHz CORDIC-based demodulation in Verilog. • Automated gas concentration retrieval using Python 1D-CNN and DMLP models trained on HITRAN-simulated WMS spectra, achieving detection precision of 1.45 ppm. • Presented an original co-authored research poster at the SRIP Symposium (July 2025) highlighting neural network filtering techniques for spectral data. Recognition: • Awarded a Letter of Recommendation by Prof. Arup Lal Chakraborty. • “Yash is a person of persistent effort... He showed discipline in his work, even when the experiments went against the plans. I consider this a notable quality for a science student.” — Prof. Arup Lal Chakraborty, Electrical Engineering, IIT Gandhinagar.