Yann Muller

Team Lead – Software-Defined Energy Network | Embedded Systems | Automotive Electronics

Toulouse, Occitanie, France

About

With extensive experience in embedded software solutions gained at major companies such as Motorola Mobility and Continental, my professional drive lies in discovering new concepts and approaches to solve complex challenges. Since the end of 2018, I have been actively contributing to a disruptive re-architecture of vehicle electronics (EE), including the introduction of Ethernet with Service-Oriented Architecture (SOA), as Release Train Architect with one of the leading players in the automotive industry. This role, as defined within the SAFe methodology, covers software, hardware, and systems topics, while also including direct customer support. I am fascinated by what technology can achieve and proud to have been part of groundbreaking concept rollouts throughout my career. This began in the mobile phone industry (11 years), working on EDGE/WCDMA technologies, and continues in the automotive world. What’s next? 😊 My specialties: - Systems Architecture (with a strong focus on software) - Project/Team Leadership experience as Product Owner for over 5 years - Embedded real-time development - Multicultural work experience (USA, Germany, Romania, India, China…)

Experience

  • NXP Semiconductors (Toulouse, Occitanie, France · On-site)
    • Team Lead – Software-Defined Energy Network | Embedded Systems | Automotive Electronics
      Jan 2025 - Present · 1 yr 6 mos

      Technical lead for the delivery of system-level solutions for NXP customers based on cutting-edge technologies such as high-side switches, eFuses, and automotive microcontrollers (S32K3xx / S32K5xx) with Ethernet, CAN, and LIN support. My work drives the adoption of 48V power architectures and addresses key system engineering and power management challenges for next-generation Software-Defined Vehicles (SDV). I drive the development of complete reference design boards, including: • System HW/SW definition with support of System architect • Embedded software architecture with support of Software architect • Responsability of engineering implementation and validation (C, assembly, real-time systems) • Test specification & validation • Guidance and supervision of PCB design, schematic reviews, and ECU development I also ensure high-quality customer support, technical documentation (user manuals, release notes, application notes), and close collaboration with cross-functional teams in a dynamic, Agile/SAFe environment. Key Skills: -Embedded Systems | Real-Time Software -Automotive Electronics | Power Distribution | 48V Architecture -Microcontrollers (S32K3xx / S32K5xx) -Ethernet / CAN / LIN -System Architecture | HW/SW Co-design -PCB Design | ECU Design -Software-Defined Vehicle (SDV) -Functional Safety (ISO 26262) -Agile / SAFe | Technical Leadership | Team Management -Customer Interface | Cross-functional Collaboration

    • Firmware Software Architect – NFC Firmware Solutions | Mobile Devices
      Aug 2022 - Jan 2025 · 2 yrs 6 mos

      Firmware Software Architect with technical leadership responsibilities for NFC firmware chips in the mobile device market. Ensuring high-quality product development through rigorous code reviews, robust software design, comprehensive documentation, and strong alignment with product and quality requirements. Working in close collaboration with Hardware teams (digital & analog), System Engineering, and cross-functional R&D groups to deliver secure, high-performance embedded solutions. Development and validation take place across both real IC platforms and virtual environments such as Windows simulations, RTL simulations, and FPGA prototypes. Key technical domains and expertise: • Embedded Security: asymmetric & symmetric cryptography, secure boot, firewalls, key management • Secure firmware architecture and low-level driver development • Non-Volatile Memory (NVM) technologies: RRAM, FLC • Anti-tearing algorithms and data integrity protection • Secure download/update processes (bootloaders, OTA concepts) • NFC standards, contactless communication, protocol stacks • Real-time embedded systems (C, assembly) • IC integration, SoC architecture, HW/SW co-design • Development flows: simulation, RTL co-simulation, FPGA, silicon bring-up • Cryptography (AES, RSA, ECC)

  • Continental (9 yrs 4 mos)
    • Release Train Architect
      Apr 2020 - Sep 2022 · 2 yrs 6 mos

      - Technical responsible of a SAFE Agile train composed by 6/7 scrum teams. - Part of Release Train architecture team (6 people) in responsibility of driving technically the whole project (+230 engineers)

    • Sw Architect Power Management
      Jan 2017 - Apr 2022 · 5 yrs 4 mos

      In parallel of Sw Function Responsible role, I have been nomintated as Sw Architect for Power Management topics for the whole business unit. This role includes following tasks : - Deliver a SW architecture document explaining how we want to architect, design and implement Power Management topics. Scope of the audience for this document is all projects accross Continental Automotive BU Body and Security - Train stakeholders - Ensure smooth integration into projects - Be the preferred contact for power management related topics

    • Software Function Responsible
      Jun 2016 - Apr 2022 · 5 yrs 11 mos

      Technical responsible of an engineering team to deliver quality focus software layers for Mode Management topics. It includes following modules : - Power Management module (characterize and implement optimized sw layer for microcontoller low power modes, evaluate current drain profiles to ensure projects achieve current drain targets...) - Ecu Manager (Autosar EcuM module) - Basic SoftWare Manager module (Autosar BswM module). For this activity to improve our efficiency, the scrum method is used within an agile context.

  • Motorola Mobility (Greater Toulouse Metropolitan Area)
    • System architecture validation for low power aspects
      Sep 2011 - May 2013 · 1 yr 9 mos

      Member of ASIC system architecture and validation team, in charge of low power hw and sw architecture system validation. Primary focus is to ensure current drain used is at lowest rate possible depending on use cases. This is done through Cadence simulations with System Verilog testbench on a complex chip (a lot of cores and microcontrollers to handshake).

    • Senior Sw Engineer
      Sep 2006 - Aug 2011 · 5 yrs

      2G-3G-LTE Senior sw engineer. I worked on drivers (C,assembly) for hardware modules in charge of communicating with RF module, so particular knowledge of digRFv3, v4, and all mechanisms to discuss with RF.

  • Motorola Mobility (3 yrs 11 mos)
    • Senior Sw Engineer - USA expatriation
      Jan 2006 - Jul 2006 · 7 mos

      Expatriation in Chicago Motorola center to increase 3G expertise and develop team synergy.

    • DSP Sw engineer
      Sep 2002 - Feb 2006 · 3 yrs 6 mos

      3G/2G Software DSP Engineer in Motorola Toulouse center. In charge of Signal processing algorithms implementation and validation (under Matlab, working on BEP (bit error probalbility), GMSK equalizer, EGPRS coder/decoder with Viterbi algorithms, 8PSK equalizer,...)

  • 6 months internship at ComOne
    Jan 2002 - Sep 2002 · 9 mos

    Mission : Analysis and conception of an electronical card for FM receiver with sw drivers