San Francisco Bay Area
• Own and lead the end-to-end High-Speed I/O strategy for the platform, spanning SerDes selection, ASIC integration, board and system design, and large-scale deployment of PCIe, Ethernet C2C fabrics. • Set technical direction for signal integrity and HSIO validation, establishing design standards, validation methodology, and quality bars from silicon through system. • Lead HSIO bring-up and post-silicon validation, guiding teams from first silicon to production readiness through structured margining, stress, and workload-driven validation. • Drive cross-functional execution across ASIC, board, firmware, and system teams, aligning decisions early to de-risk performance, scalability, and schedule. • Influence platform architecture and ecosystem choices, shaping vendor selection, technology adoption, and long-term HSIO roadmap.
FAFI | FIB | pFA | CAD | Yield | Test
• Performed end-to-end RF link budget analysis for Low Earth Orbit (LEO) satellite payloads, accounting for path loss, noise figure, gain, and system margins. • Designed and analyzed RF filtering and Low Noise Amplifier (LNA) stages, optimizing signal integrity, noise performance, and interference rejection under spaceborne constraints.