San Jose, California, United States
I'm a problem solver with a keen interest in the intersection of hardware and software. My Specialties: • Computer architecture and simulator development • ML training and inference at Scale • Programming Languages: C, C++, Python, Verilog, CUDA
Accelerating AI Inference
MI GPU Architecture Team
Recitation Instructor for the Calculus-II course. Responsibilities : • Teach recitation sections of 80+ students twice a week to supplement lectures and assist with homework problems. • Formulate and grade quizzes; Hold online office hours and give individual feedback.
Worked on the Performance architecture/verification of the Autopilot Neural Network Engine. • Added support for a new feature in a production-grade compiler targeting the AP neural network engine. • Analyzed the effects of network scaling on hardware performance by extending the in-house simulator. • Conducted performance tests on simulation, emulation and silicon to aid verification/validation tasks.
FPGA Based Test Platform • Designed a Xilinx MPSoC based test platform for Digital IPs capable of handling ATPG patterns. • Developed RTL blocks in the PL fabric to handle real-time data transfer between multiple clock domains. • Achieved a throughput of 2.56 Gbps and capability for handling 128M cycles of test pattern data. Analog IP Validation • Conducted validation, characterization and debug across PVT corners of analog IPs (I/O, DAC) • Hands-on experience with state of the art Lab instrumentation like DSOs, Logic Analyzers/Pattern Generator etc.