Mannheim, Baden-Württemberg, Germany
1. Design of the first dedicated hardware architectures for Multidimensional-LSTM and Bidirectional-LSTM neural networks 2. Development of an HLS library of low-power and low-latency parametrizable hardware architectures of CNN, LSTM, Bidirectional-LSTM, Multidimensional-LSTM, and various other DNN layers on FPGAs with full-range precision flexibility and parametrizable performance scaling 3. Integration of the first open-source HLS library of LSTM layers into the hardware library of FINN from Xilinx in cooperation with Xilinx Research Labs in Dublin https://github.com/Xilinx/LSTM-PYNQ/ 4. Development of auto machine learning for FPGAs framework based on a Neural Architecture Search (NAS), which automates both the exploration process and the implementation of optimized DNNs on an FPGA together with Fraunhofer ITWM, Germany 5. Scripts for automating hardware IP core generation, integration, and implementation 6. Implementation of FPGA accelerators designed for an early detection of atrial fibrillation for a wearable heart monitoring system, semantic segmentation, highly accurate Optical Character Recognition (OCR) 7. Implementation of a hardware-aware (quantization and pruning) training flow for various DNN topologies 8. Implementation of highly optimized software implementations of DNNs on high-performance and low-power embedded CPUs: Intel Xeon, Intel Core i, Intel Atom, ARM Cortex 9. Design of a hardware architecture of Non-Binary LDPC check node for error correction codes suitable for high-speed and low-latency wireless communication Hardware-software co-design, design of dedicated hardware architectures and hardware-aware DNN training flows C/C++, VHDL Xilinx Vivado HLS, Vivado Design Suit, Vitis, tcl scripts Python, PyTorch AVX2, SSE4, NEON, OpenMP API CUDA, OpenCL, TensorRT ZCU102, Ultra96, ZC706, PYNQ, Alveo U250 Xilinx Zynq-7000 and Zynq UltraScale+ MPSoC 65nm CMOS library from STMicroelectronics Synopsys Design Compiler, IC Compiler, PrimeTime-PX