Hyderabad, Telangana, India
As a Senior Application Engineer at Synopsys Inc., I contribute to developing SCE-MI-based transactors to enhance communication between software testbenches and RTL in hardware-software co-emulation environments. My role involves integrating RTL designs with C/C++ runtime environments, debugging transaction-level issues using Verdi tools, and optimizing emulation performance by addressing timing and partitioning challenges. I am currently pursuing a Master of Technology in Electrical and Electronics Engineering at the Birla Institute of Technology and Science, Pilani. My expertise lies in system architecture, test validation, and microelectronics, focusing on enabling efficient SoC validation and system-level debugging for large-scale designs.
Designed and developed SCE-MI based transactors to enable efficient communication between software testbenches and RTL in hardware-software co-emulation environments. Integrated RTL designs with C/C++ runtime environments using SCE-MI interfaces to accelerate SoC validation and improve test execution performance. Debugged transaction-level issues using Verdi waveform and protocol analysis tools, identifying bottlenecks and ensuring correctness of transactor-driven data exchange. Worked on debugging timing and partitioning related issues, and improving DPO and localization techniques for optimized emulation performance. Developed and maintained regression suites for validating transactor functionality and ensuring stability across multiple emulation releases. Collaborated with R&D teams to resolve performance and timing issues in co-emulation setups, enabling robust and scalable SoC validation workflows.
Validated emulation workflows and APIs supporting transaction-level modeling and XTOR-based validation. Worked extensively on ZeBu utilities and full-flow debug tools to analyze performance bottlenecks, identify inefficiencies, and improve overall runtime efficiency across complex emulation workloads. Contributed to feature enablement and release cycles by ensuring functional correctness and performance scalability across different hardware platforms through thorough validation and continuous testing efforts. Supported cross-platform validation across ORION (ZS4), ZS5, and EP1 (H100) systems.