Noida, Uttar Pradesh, India
Research and Development Engineer at Synopsys with a strong foundation in Electronics and Instrumentation Engineering from NIT Jalandhar (and an All India Rank of 95 in GATE). Currently leveraging my engineering background to contribute to cutting-edge technology solutions at Synopsys. I am deeply passionate about Digital Design and Verification, focusing on ensuring first-pass silicon success through robust verification methodologies. Languages: SystemVerilog, Verilog Methodologies: UVM (Universal Verification Methodology)