Hanoi Capital Region
40+ years of experience on ASIC and FPGA design. Board and System level design and analysis. Technical sale experience in US and ASIA PAC. Specialties: Experience hardware designer at different levels of abstraction from schematic to RTL and C/C++. Skill in Signal Integrity, EMI and board level timing analysis.
Leading Viettel verification team on deploying an advance methodology.
Lead technical team to provide exceptional design service and consultancy in design creation and verification including emulation services
Responsible to implement the equivalence system C models for DSP subsystems which are either in mathematical matlab or simulink models. Performed bit width optimization and architectural exploration in order to obtain an optimal cost and power of end result RTL architectures
Provide technical support and recommendations to existing and potential customers on adopting emulation and test bench acceleration.
Responsible to promote power and SLEC (Sequential Logic Equivalent Check) solutions at RTL and/or C levels to leading customers.