San Jose, California, United States
Introduction: I am a silicon implementation leader with more than 30 years of experience taking high-volume ASIC through sign-off and production ramp in ASIC vendor engagement and COT flows. My foundation is in-depth knowledge on Intellectual Property as well as hands-on physical design and closure: floor planning, timing constraints, synthesis-through-signoff execution, PPA trade-offs, and the discipline required to ship production-quality silicon on aggressive schedules. Across my career I have contributed to 20+ tape-outs, including ownership of multi-billion transistor chip and delivery across many generations of networking products, from tape-out through milestones such as production ramp and first customer shipment. Work Experience Overview: I bring hands-on physical design implementation and excellent program and project management skills with a strong track record of first-silicon success. I repeatedly owned physical design for large networking SoCs and taped out many generations of networking products at Cisco, and shipped production-quality silicon on schedule while aligning RTL, DFT, verification, EDA vendors, ASIC vendors, and global PD teams. Earlier roles at Sun Microsystems (technology-node driver chip, team execution), Intel (floorplan, timing, ECOs, post-silicon bring-up), and OKI (full PD flow with DFT and gate-level simulation) give me a consistent arc: PPA-aware closure, constraints/signoff discipline, and cross-functional leadership under high demand of attention and details in order to meet schedule balanced with pragmatic judgment when schedules force structured trade-offs. In my role as technical leader for Intellectual Property Management (Infrastructure & Procurement), I apply the same cross-functional muscle to ensure programs are enabled with vendor IPs, standard cells, and foundry PDKs across pre-silicon and post-silicon needs. I partner internally with Project Managers, Physical Design, Package/SI, Design, DV, and CAD Leads, and externally with foundries and IP vendors, driving integration, qualification, versioning, controlled distribution, and practical documentation/governance so teams can execute with confidence. What I'm known for technically: Top-level and Block-level implementation from power and area estimation, low-power methodology, Soft Error Rate analysis and considerations, LEC and CDC readiness, synthesis, die floor plan and constraints creation/validation through place-and-route, ECO, timing closure, STA and signoff-oriented execution and checklist tape-out readiness reviews.
IP Management — Infrastructure & Procurement: IP/PDK enablement platform and lifecycle; IP vendor and Silicon foundry engagement; qualification/release methodology; stakeholder leadership spanning PM, PD, Package/SI, DV, Design, CAD
Physical Design / Implementation): Large networking SoCs; multi-billion-transistor chips ownership; timing/PPA closure; signoff readiness; multi-party execution across RTL/DFT/verification/vendors/global PD—20+ tape-outs, eight Cisco product generations, production ramp/FCS alignment. Core Qualifications PPA-focused optimization using low-power methodology, power and area estimation, SER analysis and consideration and implementation trade-off analysis Deep familiarity with synthesis, timing constraints validation, LEC, CDC, and signoff-oriented design execution Top-level and Block physical design implementation from die floor plan through place-and-route, ECO closure, and tape-out Cross-functional leadership across RTL, DFT, post-silicon, EDA vendors, and external physical design contractors to meet schedule and quality goals Tools & Automation Comfortable in industry EDA environments for implementation using AI coding assistance with scripting/automation experience (Python/TCL) to scale repeatable workflows. If you collaborate at the intersection of silicon delivery, vendor ecosystems, and methodology, we likely speak the same language: clear ownership, measurable readiness, and communication that keeps technical truth and schedule reality aligned.