TingChiun L.

Engineering Lead - Hardware Engineering and Program Management

San Jose, California, United States

About

Networking / R&D Program Management / Hardware Design / SONiC JDM, OEM, and ODM experiences. -EDA Software: OrCAD, Allegro Viewer, Altera Quartus, Lattice Diamond. -Measurement Equipment: Oscilloscopes, Logic Analyzers, Multimeters. -Programming Languages: Verilog, Python, TTL, Bash Script. -Project/Program Management: MS Project, Smartsheet, Jira, Confluence, Arena BOM Management. -Business and Support management: Salesforce, Zendesk. I'm a highly experienced hardware engineering leader with a proven track record in high-speed networking systems and cross-functional program management. With deep technical expertise and bilingual fluency in English and Mandarin, I've successfully led complex JDM/ODM collaborations and global product launches. I take pride in bridging engineering excellence with business strategy to deliver impactful results in fast-paced, innovation-driven environments.

Experience

  • Gigamon ()
    • Principal Hardware Engineer
      Jul 2026 - Present · 1 mo

    • Sr. Staff Hardware Engineer
      Jul 2025 - Jun 2026 · 1 yr

  • Senior Director of Engineering at Micas Networks
    Oct 2022 - Jul 2025 · 2 yrs 10 mos

    • Built a pre-sales and support team for Micas, assisting account managers with customer inquiries. • Collaborated with third party to implement a support portal system for customer cases. • Worked with and supported marketing team to participate the 2023 OCP Global Summit and 2024 OCP Global Summit. • Led the team in establishing a local Proof of Concept (PoC) lab for testing and development. • Worked with cross team and brought industry product trend and customer experience for product definition. • Successfully brought Micas/Ragile products to the first recurring order customer. • Led engineering team in San Jose, California to support and achieve customer satisfaction.

  • Gigamon (11 yrs 1 mo)
    • Sr. Hardware Program Manager
      Dec 2021 - Oct 2022 · 11 mos

      • Led cross-functional teams in the technical hardware program management of various switch and module projects, ensuring successful program execution from EVT-DVT-PVT to GA. • Collaborated with internal teams, Product Line Management, HW Engineering, SW/QA Engineering, and Manufacturing/Operation, and external partners to drive the development ODM, OEM and JDM projects: - GigaVUE-TA25E, a 1RU 48 Ports/25G + 8 Ports/100G switch (ODM). - GigaVUE-TA200E, a 2RU 64 Ports/100G switch (ODM). - GigaVUE-HC1+, a 1RU modular form factor switch+NPU system and module (OEM). - > 6 Port-Pairs/10G traffic failover protection module. - GigaVUE-TA400, a 1RU 32 Ports/400G switch (JDM).

    • Sr. Staff Hardware Engineer
      Apr 2019 - Dec 2021 · 2 yrs 9 mos

      • Provided hardware technical and design support, and technical program managed for - GigaVUE-TA400, 1RU 32 Ports/400G JDM switch. 2020-2021 - GigaVUE-TA25, 1RU 48 Ports/25G + 8 Ports/100G JDM switch. 2019-2020 • Designed and program managed for OEM and JDM switch modules. 2019-2020 - GigaVUE-HC1 8 Ports/25G + 4 Ports/100G JDM module. - Designed and developed the innovative GigaVUE-HC2 GigaSmart Module. - Collaborated with CM for successful execution of GigaVUE-HC2 GigaSmart Module.

    • Staff Hardware Engineer
      Mar 2016 - Mar 2019 · 3 yrs 1 mo

      • Led the development for GigaVUE-HC1, a 1RU modular form factor switch+NPU system and modules. 2015-2019 - GigaVUE-HC1 main system (CPU+NPU+switch) - 12 Ports/10G module - 4 Ports/10G + 2 Port-Pairs/10G traffic protection module - 4 Port-Pairs/1G RJ45 traffic protection module • Designed NPU module for GigaVUE-HC2/HC2+ platform. 2018 - 2019 • Designed Atom x86 CPU board. 2017 - 2018 • Collaborated with the software team to develop Inline-bypass hardware assisting feature in Lattice MachXO2 family CPLD (2016) and Altera Cyclone V family FPGA (2017) achieving seamless integration with software functionalities. 2016-2017 • Developed innovative PPS automatic detecting/switching logic using Lattice MachXO2 family CPLD, enhancing system reliability and performance. 2016 • Collaborated with JDM CPLD/FPGA designer and the software engineers on GigaVUE-HC3 CPLD/FPGA design. 2015-2016

  • Summer Intern at Edge-Core Networks Corporation / SMC Networks
    Jun 2010 - Aug 2010 · 3 mos

    • Diagnosed, tested, and debugged RMA units for Edge-Core Networks Corporation / SMC Networks in Irvine, CA. • Collaborated with technical support team to assist customers in resolving product application issues and troubleshooting configurations. • Developed strong problem-solving skills and gained hands-on experience in customer support.