Thomas Rupp

GaN Technology Development at Infineon Technologies

Klagenfurt-Villach Area

About

In my professional career I enjoy taking up tough challenges and stepping in the lead to solve them. Project- and Task-Force (TF)-leads up to date were … • Development of SiGe-Hetero-Epitaxy for Nano-Electronics Devices with focus on Delta-Doping for 2-DEGs and local growth techniques for defect-free relaxed buffer layers. • 150nm/256Mb Trench-DRAM Development Lead-Engineer including test-site design with successful qualification of Infineons first 256Mb/150nm Trench-DRAM technology. • BCD (Bipolar-CMOS-DMOS) Transfer & Conversion including BCD Development and Qualification of Infineons first 0,6µm BCD-Technology B6CAD. • High-Temperature Processing TF-Leader in furnace and epitaxy to enable Power Technologies for bigger wafer diameters in 8-inch and beyond. • Development Project-Lead of Laser-Backside-Annealing for thin wafer processing to enable IGBT/Diode power technologies in 8-inch and beyond. • Super-Junction-MOS-FET Yield-Enhancement TF-Lead. • Understanding assembly challenges like Pick-Up and Bonding as well as MEMS devices by applying High-Speed-Imaging (HSI) techniques for analysis. • Transfer and development of HiRel Trench-MOS and GaN-HEMT Devices for space applications. IEEE Senior Member, published 25 technical papers and holding 24 patent families.

Experience

  • Infineon Technologies (27 yrs 3 mos)
    • Lead Principal Engineer GaN Technology Development
      Jul 2023 - Present · 3 yrs

      Section Head and Team-Lead for Epi, Substrates and Interfaces

    • Director High Reliability Discrete Power
      Oct 2020 - Jun 2023 · 2 yrs 9 mos

      Team- and Transfer-Project-Lead for High Reliability Discrete Power Products for Space Applications including Development for Si-MOS-FET and GaN-HEMT

    • Senior Manager High Voltage Discrete Power
      Aug 2015 - Sep 2020 · 5 yrs 2 mos

      Leading Process Integration and Product Engineering Teams for High-Voltage IGBTs, Diodes

  • R&D Senior Engineer at Siemens
    Jul 1996 - Mar 1999 · 2 yrs 9 mos

    Process Integration Engineer Mid of Line Module DRAM Development. Test-Site design and coordination for 150nm groundrule DRAM.

  • R&D Engineer and PhD Candidate at Universität der Bundeswehr München
    Oct 1995 - Jun 1996 · 9 mos

    PhD Thesis "Si-Ge Heterostructures and Devices for Nanoelectronics"

  • R&D Engineer at Siemens
    Apr 1992 - Sep 1995 · 3 yrs 6 mos

    Nanoelectronics (PIN Diodes, vertical MOS-FETs, Delta-Doping for 2DEG, local SiGe growth) SiGe Hetero-Epitaxy, Heterostructures, Superlatices, Molecular Beam Epitaxy Semiconductor processing (Epitaxy, Doping, Litho, etch, Deposition) Physical characterization (SEM/TEM, AES/SIMS/EDX, STM/AFM, RS, PL) Electrical characterization

  • R&D Engineer and Teaching Staff at University of Ulm
    Oct 1991 - Mar 1992 · 6 mos

    Ferro Electric Liquid Crystals Displays (LCDs) applying monolayers for LC alignment