Thomas Niederfriniger

Lead Principal RF/MS System Engineer in Wireless Department at Infineon Technologies

Villach, Carinthia, Austria

About

Experienced Concept Engineer with a demonstrated history of working in the semiconductors industry. Skilled in Radio Frequency (RF), CMOS, Concept Development, Technical Leadership, and Mixed Signal. Strong engineering professional with a Master of sience (Diplom Ingenieur) focused in Electrical and Electronics Engineering from Technische Universität Graz.

Experience

  • Lead Principal System Engineer at Infineon Technologies
    May 2024 - Present · 2 yrs 2 mos

    Lead Principal RF/MS System Engineer in Wireless Department at Infineon Technologies, Villach, Austria Lead of the WLS SE (System Engineering) team and the WLS WADC (ADC for Wireless) team

  • Senior RF/MS IC Design Engineering manager at MaxLinear
    Aug 2020 - May 2024 · 3 yrs 10 mos

    • RFIC Department Lead • Concept Engineering for WiFi7 RFIC • Technical lead and coordination of RF/MS design and layout team • Interface to System architects • Package design and Chip Floorplan • Chip Implementation concept • Support for RF design flow and RF tooling

  • RFIC Concept Engineer and CE-RF Team Lead at Intel Corporation
    Apr 2015 - Aug 2020 · 5 yrs 5 mos

    • Team Lead for WiFi6 RFIC Concept and DigPLL • Concept Engineering for WiFi6 RFIC • Technical lead and coordination of RF/MS design and layout team • Interface to System architects • Package design and Chip Floorplan • Chip Implementation concept • Mentor ship and training of young employees • Support for RF design flow and RF tooling

  • Concept Engineer at Lantiq
    Sep 2009 - Apr 2015 · 5 yrs 8 mos

    • Senior Staff Engineer • Concept Engineering for WLAN RF • Technical lead and coordination of RF/MS design and layout team • Interface to System architect • Implementation Specification • Package design and Floor plan • Chip Implementation concept • Mentor ship and training of young employees • Support for RF design flow and RF tooling

  • Senior Analog Design Engineer at Micronas
    Feb 2003 - Aug 2009 · 6 yrs 7 mos

    • High speed, low power AD converter, filter, amplifier and comparator design • PLL design • Elementary DC bias circuits and interface circuitry • Concept and design of: High speed data interfaces (HDMI) Analog macros for high speed video front-ends