Thomas Brandtner

Principal Engineer at Infineon Technologies

Villach, Carinthia, Austria

About

Experience

  • Infineon Technologies (26 yrs 4 mos)
    • Principal Engineer - Disruptive Analog/Mixed-Signal Design Methodology
      Oct 2020 - Present · 5 yrs 9 mos

      * Development and introduction of an „analog generator“ methodology to improve analog IP design in a revolutionary novel way * Automation of the whole workflow of analog circuit/IP design (sizing, schematic generation, layout generation, electrical simulation & verification) * Enablement to use (Gen)AI for design of analog circuits and layout * Promoting programmatic analog IC design and an analog soft-macro approach for extensive analog IP reuse * Building up a solution inside Infineon as well as a worldwide open-source community on that topic * Scrum Product Owner & Software Architect * Inspired by Berkeley Analog Generator (BAG), MAGICAL, ALIGN, and FaSOC

    • Senior Staff Engineer - Chip/Package/Board Codesign Methodology
      Aug 2016 - Oct 2020 · 4 yrs 3 mos

      Overall technical lead for chip/package/board codesign sub flow of central Infineon design system * IO pad-ring planning * Physical chip/package layout codesign * Package layout design: lead frames, laminate, FOWLP, bumping, SiP, 3D die stacks * Package DRC and LVS, ADK development * EM field simulation (quasi-static, full-wave, Spice co-simulation) * Signal integrity, Power integrity

    • Manager - Chip/Package/Board Codesign Methodology
      Feb 2011 - Jul 2016 · 5 yrs 6 mos

  • Distinguished Lecturer at Technische Universität Graz
    Feb 2007 - Present · 19 yrs 5 mos

    Courses on "Noise and Crosstalk - Modeling and Simulation" and "Selected Topics on IC Assembly"

  • External Lecturer at FACHHOCHSCHULE KÄRNTEN
    Oct 2024 - Feb 2025 · 5 mos

    Course on "Analog Design Automation" - Master program 3rd semester