Villach, Carinthia, Austria
* Development and introduction of an „analog generator“ methodology to improve analog IP design in a revolutionary novel way * Automation of the whole workflow of analog circuit/IP design (sizing, schematic generation, layout generation, electrical simulation & verification) * Enablement to use (Gen)AI for design of analog circuits and layout * Promoting programmatic analog IC design and an analog soft-macro approach for extensive analog IP reuse * Building up a solution inside Infineon as well as a worldwide open-source community on that topic * Scrum Product Owner & Software Architect * Inspired by Berkeley Analog Generator (BAG), MAGICAL, ALIGN, and FaSOC
Overall technical lead for chip/package/board codesign sub flow of central Infineon design system * IO pad-ring planning * Physical chip/package layout codesign * Package layout design: lead frames, laminate, FOWLP, bumping, SiP, 3D die stacks * Package DRC and LVS, ADK development * EM field simulation (quasi-static, full-wave, Spice co-simulation) * Signal integrity, Power integrity
Courses on "Noise and Crosstalk - Modeling and Simulation" and "Selected Topics on IC Assembly"
Course on "Analog Design Automation" - Master program 3rd semester