Taiwan
Terence Chen served as Senior R&D Engineering Manager at Siemens EDA from 2011 to 2020. Before joining Mentor Graphics (later acquired by Siemens EDA), he was a Senior R&D Department Manager at Airoha Technology, part of the MediaTek Group. He began his career as a process integration engineer at TSMC. Terence served in several positions in the Interoperable PDK Libraries (IPL) alliance and OpenPDK Coalition of Silicon Integration Initiative (Si2) in the U.S., respectively. He had led the cross-country engineering organization to work with leading foundries to setup standard PDK and reference design flow for microelectronics, photonics and MEMS. Terence has extensive expertise in silicon photonics, having developed the PIC Design Suite for photonic integrated circuit design and simulation at Latitude Design Systems, where he currently serves as CTO. At Mentor Graphics/Siemens EDA, he led technical initiatives in Silicon Photonics design flows and established photonics compact model development. His work includes creating industry-standard photonics PDKs and implementing foundry-specific design flows for silicon photonics applications. Terence's broad technical background encompasses analog/RF, silicon photonics, photonics compact modeling, MEMS, power device development, process design kit creation, tape-out sign-off procedures, and IC manufacturing processes. Terence is the lead author on 21 issued U.S. and Taiwan patents for electronic circuit simulation, semiconductor devices, and process technology.
Latitude Design Systems operates with core teams across Taiwan, Singapore, and Boston. The company is a world-leading provider of integrated optoelectronic solutions and technical services. Its flagship platform, PIC Studio, seamlessly integrates optoelectronic co-simulation, layout synthesis, and physical verification. It stands out as one of the few turnkey, all-in-one solutions on the market capable of extending its technical and service capabilities across the entire workflow, from front-end chip design and mid-end wafer manufacturing to back-end assembly, packaging, and testing. https://www.latitudeds.com/
1. Manage an engineering team and process design kit program using Scrum/Agile method with multiple customers' requests at the same time, recognizes and mitigates risks, and works proactively on contingency plans in Digital Design and Implementation Solutions Division 2. Jointly work with foundries to build up AIoT edge device reference design flows 3. Author white papers with full design flow integration 4. Coordinate with worldwide foundries, sales, internal RD and AE to provide seamless techfile support and digital PDK deliverable especially for edge AI SoC design solutions. 5. Hands-on RTL to GDS implementation including Oasys-RTL, FormalPro LEC, Tessent Scan, Nitro-SoC, Optimus-DS STA and Calibre DRC/LVS in TSMC, UMC, GLOBALFOUNDRIES, TowerJazz, TPSCo, DB Hitek, CSMC, and SilTerra technologies
Technical Focuses: - AIoT custom SoC including Tanner analog flow and digital implementation - Silicon Photonics - MEMS sensors and actuators - Hands-on Mentor IC/Photonics/MEMS design flow experience Tasks include: 1. Customer engagement to build product credibility and close deals. 2. Create formal networks involving executive level and influence senior level employees and managers in customers' and public organizations. 3. Advise senior management on specialized technical or business issues. 4. Serve as organization spokesperson on specialized market events and tech days. 5. Act as prime consultant on significant projects that affect the organization's long-term goals and objectives. Result: In PacRim region, Tanner has proven to Mentor World Trade, our management team, and our customers, that we are a leading platform for IC, MEMS and Photonics design.
- Process Design Kit development and qualification from 16nm to 500nm nodes for world-wide foundries. - Custom IC design flow development in advanced process nodes.
Manage an engineering team encompassing digital design flow deployment, device modeling and characterization, Cadence PDK development, analog/RF EDA support, foundry evaluation for new project engagement, layout team management and tapeout sign-off. Major achievements and responsibilities include: - Invent seal-ring and IO structures that are the key techniques to achieve highly integrated WiFi SoC with RF, digital baseband and power amplifier on one single die. All are US patents granted. - Invent SoC inductor structure with logic CMOS structure that enabled WiFi SoC in low cost logic CMOS process in low cost generic foundries. All are US patents granted. - Deploy digital design flow for big A/small D product - Develop RF/analog circuit blocks - Develop RF-ESD library. All are US patents granted. - Review tape-out criteria including ESD safety, signoff, and full SoC integration check-list - RFCMOS characterization, measurement and modeling development - Travel overseas to deliver RF-PDK/Model service and training course. Close $760K deal with a 5-person team. - Analog/RF back-end design and sign-off flow - Lead continual improvement activities to maximize productivity of fully custom layout by using auto-layout EDA development - Process/PDK evaluation experience includes RF/MM CMOS, SiGe, GaAs, and IPD processes.
Responsible for process development, integration engineering, and production. In charge of Taiwan major design houses and world-wide semiconductor companies. Key accounts: Philips(NXP), TI, and ADI.