Taarana Jammula

SRAM Array Design Intern @ IBM | BSE/MSE Electrical Engineering student at the University of Pennsylvania

Greater Philadelphia

About

Experience

  • Hardware Developer Intern at IBM
    May 2026 - Present · 3 mos

    SRAM dense array design team

  • Device Physics Researcher at DREL at Penn Engineering
    Sep 2025 - Present · 11 mos

    Conducting research on wurtzite/fluorite-structured ferroelectrics for non-volatile memory, collecting and analyzing I–V data from crossbar arrays to evaluate scalability, CMOS integration, and novel device configurations for improved memory performance.

  • Project Team Hardware Lead at Penn Neurotech Society
    Feb 2026 - May 2026 · 4 mos

  • Hardware Engineering AI Trainer at Handshake
    Aug 2025 - Oct 2025 · 3 mos

    Trained and evaluated Large Language Models on electrical engineering circuits and hardware concepts to improve technical reasoning and accuracy

  • PDP Electrical Engineering Intern at BASF
    May 2025 - Aug 2025 · 4 mos

    - Conducted comprehensive power system studies using SKM Power*Tools, including Arc Flash hazard analysis, short circuit current evaluations, and time-current coordination adjustments; identified and mitigated NEC code violations in facility one-line diagrams - Documented grounding and bonding configurations across BASF plant sites, contributing to electrical safety compliance; explored Electrical Area Classification to support risk assessments and ensure alignment with NFPA and OSHA standards - Gained exposure to PLC programming (ladder logic) and HMI design, working with automation systems controlling belt lines, extruders, tank farms, and other large-scale industrial equipment in a chemical plant