Kuala Lumpur, Federal Territory of Kuala Lumpur, Malaysia
Experienced R&D Engineer specializing in FPGA software device modelling with ~10 years of experience (compilation and verification). Proficient in multiple programming languages (C++, Python, PERL, TCL, HW TCL) and hardware description language (Verilog, System Verilog, VHDL). Demonstrated expertise in debugging, problem-solving, brainstorming innovative ideas, facilitating cross departmental discussion (include cross site), project transfer, leading team and mentoring junior engineers. Strong believer and committed to continues learning. Always find ways to improve and challenge existing approach to develop cutting-edge software solutions. I am committed to fostering overall team growth through coaching and mentoring, ensuring that every team member can contribute at their highest level.
Specialize in FPGA device modelling. - Become DSP lead by leading a group of junior/new Engineer to develop DSP AI Tensor mode and delivered all committed features within the challenging date line which became the main revenue generator for the company toward AI platform. - Conduct technical discussion and 1-1 mentoring for junior engineers in technical and softskill trainings. - Introduce various data-driven solutions to help improve team efficiency and overall Software tool quality. - Engage various engineering team within site and cross site. - Actively participate and write technical paper for in house Technical forum with 3 submitted paper are accepted for official publication. - Work and involve in other blocks within FPGA as well example peripheral and other core blocks support
- Expand the DSP megafunction/IP charter to include responsibilities for DSP block (Fixed Point and Floating Point) development, focusing on Quartus atom bring-up, synthesis, fitting, placement, routing, simulation flow, and timing analysis. Collaborate with the cross-site hardware team to discuss and understand hardware-supported features, and define the necessary changes for device modeling. - Define and create comprehensive test cases based on block features to ensure that all specified features in the hardware specification documentation are fully tested and verified. Testbench and reference model creation to verify test designs. - Develop and document block and IP features, including detailed test plans. Provide technical support and troubleshooting/debugging assistance for issues raised by cross-functional teams or customers.
Software Device Modeling Engineer Specializing in Digital Signal Processing (DSP) Megafunction/IP Development - Spearhead the development and management of DSP megafunction/IP (lpm_mult, altmult_complex, altera_mult_add and family specific native IP) in the Quartus IP Catalog, driving innovative solutions and ensuring high-performance standards. - Maintained the highest quality of DSP IP by integrating the latest device features and conducting rigorous compilation and simulation verification. - Actively addressed and resolve customer issues related to DSP IP prompt and effective feedback, ensuring exceptional customer satisfaction and reliability of delivered solutions.