Cranston, Rhode Island, United States
I have been with NXP since the spring of 2022, where I manage a team of SoC Architects assigned to Automotive MCUs and became a Fellow in 2024. In this role I have found a impactful way to apply my experience in SoC Design and Architecture, Innovation, Project Management, People Management, Rapid Prototyping, and Customer Engagement. With a focus on use-case driven MCU Architecture and bringing AI solutions to the MCU edge, we are innovating on both the product technologies and the definition methodologies. In the summer of 2017, I and five of the brightest engineers I've ever worked with founded Dover Microsystems. As CTO, I lead the design of a coprocessor solution to finally put an end to cyber attacks. We do this by building security into the processor architecture, enabling the processor to understand code intent, flow, and type information at every instruction to stop an attack before it starts. This technology builds off 7 years of research by DARPA and Draper Labs, where I worked on the project for one year before spinning off Dover. Previously I was an SOC Architect for the Wireless Systems Group of Microchip Technologies. I joined Microchip in 2010, and helped create the Program Management group before transitioning into Architecture. After working in Arizona for two years, they were gracious enough to enable me to continue as a remote worker so that I could move my family home to raise my daughter around her extended family. Prior to Microchip, I worked for 2.5 years at Qualcomm in Boxborough, MA, a relatively small remote office. At Qualcomm I worked on CDMA and UMTS Modem design in RTL. Before Qualcomm I worked at Draper Laboratory in Cambridge MA as an Embedded Systems Engineer, with tasks including conceptualizing, specification, breadboarding, FPGA programming, firmware development, MCM layout, testing, qualification, and fielding. I've worked for 2 other startups, one in MA and one in FL, each culminating in first-pass silicon successes. At Authentec, my fingerprint sensor became the foundation of TouchID when Apples acquired them. I'm a huge fan of fingerprint sensors now and am hopeful that the concept will thrive here in the US as it well as it has abroad. Specialties: SOC Architecture for micro-controller designs. Project Management with skills in product definition, cost analysis, scheduling, and resourcing. Digital design in System Verilog. Rapid prototyping of embedded systems Over-exuberant use of Python scripting
Hardware Architect of the Inherently Secure Dover Processor.
As a senior member of the Wireless Solutions Group, I am responsible for architecture definition of next generation micro-controller and micro-processor SoC(s) with wireless connectivity targeting the broad embedded market space. I explore relevant ULP technologies and architecture concepts, performance and cost considerations and integrate them into innovative, cohesive architecture definitions. In addition, developing detailed design objective specifications is one of the primary key responsibilities. The output of this effort provides critical input into the design teams to design, implement, and stream out the chip. I participate and contribute in new product development meetings to work with Application team, Software Architects, and Marketing team to evaluate future SoC trends with Bluetooth/WiFi connectivity.
Program Manager for 32-bit Microcontroller SOC products. As a Program Manager, I lead the product definition process with Marketing, Architecture, Applications, Verification, Development Tools, and Production/Test Engineering. Once defined and accepted by upper management, I lead the design cycle for digital, analog, synthesis, APR, and layout from conception through tape-out. During this process I create and track schedules and assignments, regression status, bugs and issues, and IP acquirements. I have transitioned the Program Management team to a new scheduling methodology following the Critical-Chain concepts of Theory of Contraints Program Management. Currently on third design successfully utilizing this methodology to achieve an on-time tape-out, with better communication up the management chain in the process. Received Recognition Award for designing new flash architecture saving 3 Cents of COGS on 16-bit DSPic Product Received Recognition Award for implementing Derivative Project Flow to dramatically reduce cycle time for memory/peripheral product derivative tape-outs.
Task Lead for Vector Processor Engine and Demodulation Front-end design on new MSM modem to incorporate UMTS Rel9 specs. Designed transmit half of CSM8700's CDMA200 base station modem, quadrupling channel capacity from previous design and adding CMDA200 RevE features for improved capacity.