Stephane Boisclair

Senior Principal Engineer

Berlin Metropolitan Area

About

Over twenty years of extensive ASIC, FPGA and Hardware design experience in Telecommunication, Video encoding/decoding and Industrial product development. Experienced to work on multi-sites and international projects. Specialties: ASIC/FPGA Design and Verification using System Verilog/VHDL, Product definition, Architecture, High level design, IP specification, Simulation, Synthesis, Floorplanning, Timing Analysis and DFT.

Experience

  • Senior Principal Engineer at Rambus
    May 2022 - Present · 4 yrs 3 mos

  • Senior Hardware Designer at Hardent
    Dec 2003 - May 2022 · 18 yrs 6 mos

    ASIC/FPGA and Hardware Development for Industrial, Telecommunication and Video encoding/decoding projects.

  • Teacher, Electrical Engineering at College Ahuntsic (Montreal)
    2004 - 2005 · 1 yr

    Topics teached: Programmable Logic Controllers, Electronic AC/DC Circuits and Electrical Motors

  • ASIC Consultant at Texas Instruments Inc. (Nice)
    2003 - 2003 · Less than a year

    Development of ASIC Test Strategy (Scan, DFT, BIST) for OMAP Processors

  • Senior Product Designer at PMC-Sierra Inc. (Montreal)
    1999 - 2002 · 3 yrs

    Design and Verification of SONET/SDH and 10GbE/GbE Ethernet ASICs