Kowloon, Hong Kong SAR
Currently work as a digital design engineer at Huawei HKRC. I obtained my Master's degree in Electrical Engineering at NU, after completing my Bachelor's degree in Electronic and Information Engineering at The Hong Kong Polytechnic University. My core competencies include Computer architecture, Verilog, SystemVerilog and VHDL. In my courseworks at NU, I gained practical experience in FPGA development with VHDL, and implemented Universal Verification Methodology(UVM) with SystenVerilog. Meanwhile, I became familiar with the softwares including Quartus, Simplify, and Modelsim. Besides, my project experience in Computer Architecture made me familiar with the RISC-V CPU structure, the front-end to back-end Digital design flow, and the EDA tools including Xcelium, Genus, and Innovus.
NPU design and optimization
- Design error detection circuits to detect the set-up timing violations in the critical path of different CPU pipeline stages. - Tape out the design based on a 32-bit dual-issue RISC-V CPU. - Implement Openlane for EDA and OpenRAM for generating SRAMs