Bengaluru, Karnataka, India
Experienced Low Power Engineer and founding member of the Power teams at Google Silicon and SiFive India, with end-to-end expertise in optimizing power efficiency—from defining product specifications to driving power reductions across architecture, RTL, and physical design stages. Specialized in achieving competitive power targets and maximizing performance-per-watt (Perf/W) across high-performance compute IPs, including ARM and RISC-V CPUs, and TPU subsystems. Skilled in architecting power methodologies, developing automated tool flows to identify and address pre-silicon power weaknesses, and collaborating with cross-functional teams across Architecture, DV, Physical Design, Software, Thermal, EMIR, SoC, Validation, and Post-Silicon. Proven track record of achieving <2% silicon correlation across multiple IPs, use cases, and DVFS scenarios, ensuring designs meet power goals while optimizing PPA (Power, Performance, Area) throughout the product development lifecycle.
• As one of the first hires of the team, owned CAD workflows, frontend and backend power analysis, third party tool assessments, methodologies for Power, designed and developed aa fully functional push-button flow for power analysis incorporating multiple tools ( PTPX Primepower; Power Replay; Power Artist; PrimePower RTL) with proven Silicon correlation within 2% across multiple use cases for different CPU IPs. • Engaged in perf/W analysis and influencing product specs for power, converging to aggressive top to bottom power targets for vector units, SiFive-Essential and SiFive-Intelligence Out-of-Order family of cores. • Achieved 25-30% peak active use case power reduction through RTL power bugs,10-15% in DoU use cases and 70-80 % in idle use dynamic power alongwith 10-15% through implementation methodologies with support from PD teams. • In-house scripts and tools development for clock tree weaknesses, recovery methodologies, liberty profiling for PPA, tech scaling/comparisons and design profiling etc. • Lateral hiring and team building.
• First Hire at gChips (Google Silicon) for Power; Led development of power flows and methodologies from the ground up for Power and related domains. • Led power signoff and convergence across multiple IPs (CPU, TPU, GPU) in Tensor SoC Gen1-3, powering Pixel devices. • Achieved 10-25% power reduction across IPs and ~90% CPU idle power reduction by identifying architectural power bugs. • Worked closely with multiple cross-functions across CAD, DV, PD, STA, PMIC, EMIR, Package, Post-Silicon, VI, and third-party vendors. • Represented Google at campus pre-placement talks, hired interns and early-career talent, and led lateral hiring efforts.
• Responsible for Power Signoff, Optimisation and analysis for CPUSS for MSM (Premium; Mid and Value tiers) and MDM • Expertise in PTPX, PrimePower and PrimeTime • Deep dive with Post Si teams to understand/analyze split parts data for process impact on IDDq (ON/OFF), VMIN and FMAX. • Establishing competitive power targets for CPU subsystem through power reviews and achieving the same in collaboration with Physical Design, Architecture and DoU teams. • Responsible for thermal signoff, CPU power modeling, Post Silicon power correlation, CPU PDN for Static and Dynamic IR analysis , SoC, Software teams and scenario analysis (e.g., DoU, thermal, transient, IR drop) to optimize performance and power efficiency across various DVFS-Low Power modes. • Mentorship and cross team knowledge exchange