United States
• Floorplan for blocks with multiple power domains, feedthroughs, analog and digital IPs, high macro count, etc. • PnR execution for multiple TILES - blocks (4nm,5nm,7nm) from floorplan to GDS with power, performance and area optimization. , • Participated in block closure in various signoff domains delivering the best quality. • Support and debug in methodology development. • Handling multiple blocks in a single project. • Leading other blocks. • Mentoring Juniors and Knowledge Transfer to lateral entries. • Successfully completed several tape-outs under fast paced design environment with tough deadlines. • Design and implementation of functional unit blocks for microprocessor core in latest technology node (14nm) using semi-custom design tools. • Static timing analysis (STA), functional equivalence verification (FEV), timing closure, power reduction, clock tree synthesis, design optimization, were part of work. • Responsible for designing and implementing modules from data path specifications. • Design implementation and optimization of functional unit blocks of microprocessor core and drive them to signoff with timing closure (STA), power reduction and quality.