Bengaluru, Karnataka, India
Physical Design Engineer, experience in ASIC implementation, skilled in advanced nodes between (10nm to 32nm). Proficient in the end-to-end PD flow from Synthesis to GDSII, including floorplanning, power planning, placement & routing (PnR), CTS, STA, timing closure, and sign-off. Strong expertise in physical verification (DRC, LVS, ERC, IR drop, EM, antenna effect fixing) and ECO implementation for timing and signal integrity. Hands-on with industry-standard EDA tools (Cadence Innovus, Calibre, Tempus ,ICC2, Primetime, StarRC) and experienced in handling large-scale block-level designs. Passionate about delivering optimized, high-performance, and reliable chip designs while continuously enhancing technical skills. with following skills 1) Linux and scripting (shell,perl, TCL/tk). 2) Advanced Logic Design. RTL to GDS 3) Fundamentals of Static Timing Analysis. 4) Understanding of ASIC design flow. 5) Setup and Hold timing violations fixed. 6) Chip-Level and Block-level implementation steps. 7) Floorplan and power planning. 8) Placement and Clock Tree Synthesis . 9) Routing. Physical Verification DRC, LVS and DFM checks and fixed. 10)Signal Integrity and Back annotation. 11) Sign-off checks and Tapeout . 12) Concept to Chip design flow for small, large and Analog mixed signals. 13) EM/ IR Analysis and fixed. 14) Latch up issues fixed. 15) Basic to Advanced Static timing analysis (STA) setup and hold time, CDC, HVT,LVT SVT,PVT/RC OCV,AOCV,CRPR/CPPR. 16) Crosstalk effect and crosstalk noise fixed. 17) TOOL USED: Cadence Innovus, Calibre, Tempus, ICC-II, Primetime, DC,
Embedded systems design & IoT