Sharada Yeluri

Engineering Leader

Cupertino, California, United States

About

A seasoned leader with over 25 years of rich experience in high-performance networking ASICs/CPUs and systems. Successfully defined, led, and delivered countless high-performance, first-time functional silicon chips.

Experience

  • Vice President of Engineering at Upscale AI
    Apr 2026 - Present · 3 mos

  • AVP of Engineering, Scale-Up Fabrics at Astera Labs
    May 2025 - Apr 2026 · 1 yr

  • Sr. Director of Engineering at Juniper Networks
    May 2000 - May 2025 · 25 yrs 1 mo

    Project head/leader for Express family routing ASICS used in PTX routers. Lead several generations of Trio PFE chips before that.

  • Senior Design Engineer at Sun Microsystems
    1995 - 2000 · 5 yrs