Leuven, Flemish Region, Belgium
Experienced R&D engineer working on process integration of STT and SOT Magnetic Memory and two terminal selector devices for MRAM concepts, and technology pathfinding. 4 years of semiconductor experience, including process integration, package, and wafer-level integration and characterization testing, and failure analysis to determine the root cause. Demonstrated ability to solve multiple semiconductor challenges, ranging from device enablement to reliability and yield increase.
- Owner of TMR sensor project from design to process integration and development. - Owner and coordinator of STT & SOT MRAM, 2 terminal selectors for MRAM devices and IGZO for DRAM - planning and project management of deliverables, resources, and communication with partners: - MRAM & IGZO transistor Vehicle owner: development, debug, and optimization: Responsible of lot start, planning and follow up. Close collaboration with process developers for maintenance and optimization of process bricks (Etch/litho/CMP/Thin-film/metro) - Mask set design, Etch/litho/CMP/Thin-film/metro processes planning and development.
Optimization study of SAMs (Self-Assembled Monolayers) passivation process of Copper microbumps for 3D stacking of Si chips
Development of a process for the filling of TSVs and the exposure and development of wave-guide line structure for wafer connection of TSVs
System level optimization of feed-forward equalizers for laser drivers