Greater Barcelona Metropolitan Area
My research interests focus on the field of processor architectures, multi- and many-core processors hardware design and software programming paradigms.
Architecural design and RTL development of data cache and coherent memory subsystem and bus interfaces for RISC-V processor cores in Semidynamics' portfolio.
At Recore Systems I am in charge of developing a fully custom IP aimed at real-time big data analysis and feature storage/extraction. The IP has been developed from scratch and has currently reached a marketable maturity level. Among the development of the IP, the work requires extending and adapting a fully-custom many-FPGA architecture, taking care of custom interconnects, communication paradigms, performance analysis and inspection of potential bottlenecks. -Skills: architectural specification, design implementation and mentoring of fellow team members; verification both pre- and post-implementation; integration of IP on final product. -FPGA full-stack development and testing.
At Imagination Technologies I have been working in a dedicated project team, with responsibilities covering: design specification, RTL coding and verification of video-processing IPs. -Skills: Optimisation and porting to hardware of multimedia (image/video) processing algorithms, full front-end development. Verification flow from RTL to post-implementation. -FPGA system-level prototyping and testing. -Advanced notions of formal verification (Cadence suite).
During my PhD studies I have been involved in research activities, mostly inside the framework of a FP7 European-funded project (MADNESS FP7). The work I developed during this period involved: -FPGA prototyping of different multi-core architectural configurations, analysis and optimization of algorithms and applications for VLIW full-custom multi-core architectures; -Multi-Core heterogeneous computing architectures, FPGA-based technology-aware prototyping support for system-level Design Space Exploration; -Fully-customizable VLIW processor architectures, RTL code generation/integration/implementation and application porting; -RTL coding/debugging (Verilog and VHDL). Beyond these activities, I have been producing documentation and deliverables accounting for the work carried under the project grant, including participation at meetings with partners and presentation/dissemination of the achieved results.