Minneapolis, Minnesota, United States
My technical skills encompass many EDA tools, including Synopsys ICC2, Fusion Compiler, Prime Time, ICV, HSPICE, Cadence Innovus, Genus, Tempus, and Virtuoso Suite. I am proficient in TCL, Shell Script, and UNIX utilities, and have hands-on experience with technology nodes ranging from 3nm to 180nm. I am passionate about leveraging my skills and experience to drive innovation and excellence in VLSI design and physical design implementation. I am open to opportunities that challenge me to apply my technical expertise and leadership skills to deliver high-quality results. Expertise in FloorPlan, Power planning, Placement, Timing Optimization, Clock Tree Synthesis, Routing, Timing, Setup and Hold Fixes, and sign-off.
Microelectronics Co-design Research Group with Prof. Yu (Kevin) Cao
EE 5324: VLSI Design II | By Prof. Yang (Katie) Zhao | Spring 2025 CMOS arithmetic logic units, high-speed carry chains, and fast CMOS multipliers. High-speed performance parallel shifters. CMOS memory cells, array structures, read/write circuits. Design for testability, including scan design and built-in self-test. VLSI case studies. EE 2301: Introduction to Digital System Design | By Prof. Ulya Karpuzcu | Spring 2025 Boolean algebra, logic gates, combinational logic, logic simplification, sequential logic, design of synchronous sequential logic, Verilog modeling, design of logic circuits. Integral lab. EE 5323: VLSI Design I | By Prof. Yu (Kevin) Cao | Fall 2024 Combinational static CMOS circuits. Transmission gate networks. Clocking strategies, sequential circuits. CMOS process flows, design rules, and structured layout techniques. Dynamic circuits, including Domino CMOS and DCVS. Performance analysis, design optimization, and device sizing. EE 1301: Introduction to Computing Systems | By John Sartori | Fall 2024 C/C++ programming constructs, binary arithmetic and bit manipulation, data representation, and abstraction, data types/structures, arrays, pointer addressing, control flow, iteration, recursion, file I/O, and basics of object-oriented programming. An Internet-of-Things lab is integral to the course.
Technical Lead
Santa Clara, Calif. (May 20, 2019) – Marvell (NASDAQ: MRVL) today announced it has entered into definitive agreements to purchase Avera Semiconductor, the Application Specific Integrated Circuit (ASIC) business of GLOBALFOUNDRIES.
• Executed block-level floorplanning, macro placement, pin planning, power planning, placement, CTS, routing, and post-route optimization to enable hierarchical SoC closure. • Achieved multi-mode multi-corner static timing closure using Synopsys PrimeTime and Tweaker, resolving setup/hold violations through targeted ECO implementation, sizing, buffering, Vt swaps, and useful-skew optimization. • Closed tapeout-critical signoff issues across DRC, LVS, DFM, EM/IR, SI/crosstalk, antenna, DRV, timing, and formal equivalence before final GDSII handoff.