Satwinder Singh

Verification Leader | Senior Manager – Functional Verification | Building & Scaling Global DV Organisations | CPU, ADAS, NVM, Automotive MC

Greater Bristol Area, United Kingdom

About

Senior Verification Manager with 22+ years of experience delivering complex silicon across automotive microcontrollers, SoCs, CPUs, ADAS radar accelerators, and memory subsystems. I currently lead organisational strategy and execution for functional verification across compute and memory platforms, building and scaling high-performing global DV teams that deliver predictable, metrics-driven silicon outcomes. My focus is on combining deep technical credibility with strong organisational leadership — enabling teams to achieve first-pass silicon success while continuously improving productivity, quality, and delivery predictability. Core areas of impact : - Global verification strategy and organisational scaling - End-to-end DV lifecycle ownership and tape-out readiness - Metrics-driven verification (coverage, bug funnels, CI/CD health) - ISO 26262 safety-compliant verification - Agile transformation and distributed delivery models - ODC partner governance and capacity scaling - Methodology, automation, and infrastructure transformation Across my career at Infineon and earlier roles, I have led verification for complex CPU, ADAS, NVM, and system IP programs, while building reusable UVM environments and driving organisation-wide quality improvements. I welcome connections with semiconductor leaders, and peers working on advanced silicon across diverse platforms.

Experience

  • Infineon Technologies (16 yrs 5 mos)
    • Engineering Manager - Compute, NVM & Memories
      Oct 2024 - Present · 1 yr 10 mos

    • System IP & NVM Verification Manager
      Feb 2022 - Oct 2024 · 2 yrs 9 mos

    • Lead / Principal Engineer, CPU & ADAS Verification
      Apr 2012 - Feb 2022 · 9 yrs 11 mos

  • Staff R&D Engineer, Verification at IBM India Pvt Ltd
    Oct 2009 - Mar 2010 · 6 mos

    Processor Development

  • Sr. Verification Engineer at AMD
    Apr 2008 - Dec 2009 · 1 yr 9 mos

  • Freescale Semiconductor (4 yrs 3 mos)
    • Senior Design Verification Engineer
      Jan 2004 - Mar 2008 · 4 yrs 3 mos

    • Design Verification Engineer
      Jan 2004 - Mar 2008 · 4 yrs 3 mos